The storage capacity of semiconductor memory devices as represented by DRAM (dynamic random access memories) has increased each year as a result of the progress made in microfabrication techniques. However, as miniaturization has progressed, there has also been an increase in the number of defective memory cells contained in a single chip. Such defective memory cells are ordinarily replaced into redundant memory cells; in this way, defective addresses are relieved.
Generally, defective addresses are stored in fuse circuits that include a plurality of program fuses. In a fuse circuit, a match signal is activated when access to these addresses is requested. When the match signal is activated, the pre-decoder generates a signal in which a substitute address is pre-decoded rather than the input address. Redundant memory cells, rather than defective memory cells, are thereby accessed, and defective addresses are accordingly relieved.
FIG. 8 is a block diagram showing the main parts of a conventional semiconductor memory device.
The semiconductor memory device shown in FIG. 8 includes a memory cell array 10, and an access control circuit 20 for accessing the memory cell array 10. The access control circuit 20 includes a pre-decoder 21 which pre-decodes the input address ADD, a driver 22 which receives the output of the pre-decoder 21 and selects specified memory cells, and a fuse circuit 23 which stores the addresses of defective memory cells.
In cases in which the input address ADD is not the address of a defective memory cell, i.e., in cases in which this address is a normal address, the pre-decoder 21 pre-decodes the input address ADD directly, and supplies the output to the driver 22. On the other hand, in cases in which the input address ADD is the address of a defective memory cell, i.e., if this address is a defective address, the fuse circuit 23 activates a match signal 23a. The match signal 23a is input to the pre-decoder 21. When the match signal 23a is activated, the pre-decoder 21 generates a pre-decoded address that is substituted using internal substitution logic 21a. 
Furthermore, regarding the storage of addresses, the techniques described in Japanese Patent Application Laid-Open Nos. 2001-358296 and H9-7390, and U.S. Pat. No. 5,267,213 are known.
However, in order to detect a defective address using the fuse circuit 23 and generate a pre-decoded address that is substituted using the pre-decoder 21, a specified operating time is necessary. In particular, since the substitution logic 21a contained in the pre-decoder 21 includes numerous gate circuits, it takes a relatively long time for signals to pass through. Accordingly, the access speed is limited mainly by the pre-decoder 21, and this is an obstacle to high-speed access.